Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has a first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed, wherein the second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with the control signal which was responded to when the second power supply state was instructed by the third circuit block to the first circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent applicationNo. 2004-124683 filed on Apr. 20, 2004, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice, and more particularly to a technique that can be effectivelyapplied to, for instance, a system-large scale integrated circuit (LSI)in which each of a plurality of functional modules is divided intocircuit blocks and power supplied is turned on or off according to theoperation or non-operation of each functional module.

There is Japanese Unexamined Patent Publication No. 2002-026711, whichdiscloses a configuration in which the circuit is divided into a circuitblock consisting of a MOSFET having a low threshold voltage and acircuit block consisting of a MOSFET having a high threshold voltage,the leak current is reduced by cutting off power supply to the circuitblocks of the low threshold voltage in the standby mode when thesemiconductor integrated circuit device is not operating, and a gatecircuit known as a wrapper is provided on the route on which its inputsignals and output signals are communicated. Also, the existence ofJapanese Unexamined Patent Publication No. 2003-218682 is reported,which discloses a configuration comprising a sending-side circuit blockhaving a power switch, a receiving-side circuit block, and a micro I/Ocircuit for supplying output signals from the sending-side circuit blockto the receiving-side circuit block as input signals, in which the microI/O circuit prevents the output signals from being propagated with acontrol signal from the receiving-side circuit block when power supplyto the sending-side circuit block is cutoff by the power switch. Howeverneither of these patent references makes any mention of technicalproblems the invention under this application intends to solve.

[Patent Reference 1] Japanese Unexamined Patent Publication No.2002-026711

[Patent Reference 2] Japanese Unexamined Patent Publication No.2003-218682

SUMMARY OF THE INVENTION

According to Patent Reference 1, the whole LSI is divided into alow-threshold voltage circuit block and a high-threshold voltage circuitblock and a leak current is reduced by cutting off power supply to thelow-threshold voltage circuit block when the LSI is in the standby mode.Therefore, where a plurality of functions are mounted on a singlesemiconductor integrated circuit device as in a system LSI and there areboth operating functional blocks and non-operating functional blocks,the above-stated technique of power saving by cutting off power supplyto non-operating functional blocks cannot be applied. On the other hand,Patent Reference 2 discloses a configuration in which the circuit isdivided into functional blocks, and power supply to standing-by circuitblocks is cut off. However, this configuration requires a specialcircuit block to connect the two circuit blocks, i.e. the micro I/Ocircuit, to prevent the through current, which would arise in thecircuit block to which power is supplied as a result of the floating ofthe output signals of the circuit block to which power supply has beencut off. This is also true of the configuration according to PatentReference 1, wherein the low-threshold voltage circuit block to whichpower supply is cut off is provided with circuit blocks known as anoutput wrapper and an input wrapper.

These configurations in which are arranged, apart from circuit blocks toperform the essential functions of the circuit, circuit blocks whichprevent unfixed signals in the circuit block to which power supply hasbeen cut off is prevented from being transmitted to the circuit block towhich power is supplied, such as the wrapper and the micro I/O circuit,involve a problem of increased man-hours spent on the designing ofcircuit block arrangement for that purpose. Especially the configurationaccording to Patent Reference 2 involves a problem of requiringdifferent ways of control to match four cases of power cut-off, asstated in paragraph 0020 of the specification, because where the microI/O circuit has a level changing function, the earlier stage is suppliedwith the same source voltage as the sending-side circuit block and thelater stage is supplied with the same source voltage as thereceiving-side circuit block, with the consequence that one circuitblock is supplied with a common source voltage to a different circuitblock.

An object of the present invention is to provide a semiconductorintegrated circuit device which achieves multi-functionalization andpower saving with a simple configuration. Another object of theinvention is to provide semiconductor integrated circuit device enhancedin design efficiency while achieving multi-functionalization and powersaving. The aforementioned and other objects and novel features of theinvention will become apparent from the following description in thisspecification when taken in conjunction with the accompanying drawings.

To briefly describe a typical aspect of the invention disclosed in thepresent application, the semiconductor integrated circuit device hasfirst through third circuit blocks, wherein the first circuit block hasa first power supply state in which the operation of internal circuitsis guaranteed in accordance with an instruction from the third circuitblock and a second power supply state in which the operation of theinternal circuits is not guaranteed, the second circuit block has aninput unit which receives signals supplied from the first circuit block,and the input unit of the second circuit block has an input circuitwhich, in accordance with the control signal which was responded to whenthe second power supply state was instructed by the third circuit blockto the first circuit block, causes a specific signal level to bemaintained in compliance with the operating voltage of the secondcircuit block irrespective of the signal supplied from the first circuitblock.

With a simple configuration, inputs at unfixed levels to a circuit blockin an operating state can be prevented while saving power consumption byinterrupting power supply to a standing-by circuit block. The controlsignal for the prevention of inputs at unfixed levels can be easilygenerated and matched with power cut-off control.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 show the configurations of the smallest unit of a semiconductorintegrated circuit device, which is a preferred embodiment of thepresent invention.

FIG. 2 is a timing chart illustrating the operation of the circuit block3 in FIG. 1.

FIG. 3 is an overall block diagram of a semiconductor integrated circuitdevice, which is a preferred embodiment of the invention.

FIG. 4 is a circuit diagram of an example of input circuit provided inthe micro input/output circuit of FIG. 3.

FIG. 5 shows the configurations of the smallest units of anothersemiconductor integrated circuit device pertaining to the invention.

FIG. 6 is a waveform chart illustrating an example of operation of thecircuit embodying the invention, shown in FIG. 5,

FIG. 7 are block diagrams illustrating an example of operating form ofan input circuit for preventing the propagation of unfixed levelsaccording to the invention.

FIG. 8 are block diagrams illustrating another example of operating formof an input circuit for preventing the propagation of unfixed levelsaccording to the invention.

FIG. 9 is a timing chart illustrating an example of standby shiftingsequence of a specific circuit block in a semiconductor integratedcircuit device embodying the invention.

FIG. 10 is a timing chart illustrating an example of return from standbysequence of the specific circuit block in the semiconductor integratedcircuit device pertaining to the invention.

FIG. 11 is a schematic block diagram of a whole system pertaining to theinvention corresponding to FIG. 10 and FIG. 11.

FIG. 12 is a schematic block diagram of a semiconductor integratedcircuit device pertaining to the invention.

FIG. 13 is a schematic block diagram of another semiconductor integratedcircuit device pertaining to the invention.

FIG. 14 is a schematic block diagram of still another semiconductorintegrated circuit device pertaining to the invention.

FIG. 15 is a schematic layout of a semiconductor integrated circuitdevice pertaining to the invention.

FIG. 16 is a layout of one example of power supply lines matching thevdd-supplied logical unit 2 in FIG. 15.

FIG. 17 is a schematic layout of one example of lower part of the powersupply line matching the vdd-supplied logical unit 1 in FIG. 15.

FIG. 18 is a circuit diagram illustrating the relationship among thepower supply SW controller (PSWC), the power supply SW and the internallogic in FIG. 17.

FIG. 19 is a schematic layout of one example of cell C in FIG. 16.

FIG. 20 is a schematic layout of one example of power supply line of thesemiconductor integrated circuit device pertaining to the invention.

FIG. 21 is a circuit diagram of one example of step-down power supplycircuit to be mounted on the semiconductor integrated circuit devicepertaining to the invention.

FIG. 22 is a circuit diagram of another example of step-down powersupply circuit to be mounted on the semiconductor integrated circuitdevice pertaining to the invention.

FIG. 23 is an overall block diagram of another example of semiconductorintegrated circuit device pertaining to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 show the configurations of the smallest unit of a semiconductorintegrated circuit device, which is a preferred embodiment of thepresent invention. FIG. 1(A) shows one example of one type of operatingstate, and FIG. 1(B), one example of another type of operating state.The smallest unit of the semiconductor integrated circuit device of thisembodiment consists of three circuit blocks. A circuit block 1, turnedoff in a standby state, is provided with a power switch. A circuit block2 has a circuit portion which operates in response to a signal from thecircuit block 1. The presence or absence of the function of turning offwhen standing by is irrelevant to the circuit block 2. The circuit block1 is provided with a circuit block 3 which generates a control signalSWC for power supply control and a control signal INC for preventingpropagation of unfixed levels from a circuit block to which power supplyis turned off. Power supply to this circuit block 3 is on all the time.An input circuit for receiving signals from the circuit block 1 isprovided in the circuit block 2. The input circuit is composed, as itsillustrative example, of logical gate circuits including a latch circuitFF, a NAND circuit G1 and a NOR circuit G2.

Referring to FIG. 1(A), both of the circuit blocks 1 and 2 are placed inan operating state. Thus, the power supply control signal SWCtransmitted from the circuit block 3 causes power to be supplied to thecircuit block 1. The control signal INC for preventing propagation ofunfixed levels transmitted from the circuit block 3 causes the inputcircuit provided in the circuit block 2 to capture signals transmittedfrom the circuit block 1.

Referring to FIG. 1(B), the circuit block 1 is placed in a non-operatingstate, and the circuit block 2 is placed in an operating state. Thus,the power supply control signal SWC transmitted from the circuit block 3cuts off power supply to the circuit block 1. The control signal INC forpreventing propagation of unfixed levels transmitted from the circuitblock 3 causes the input circuit provided in the circuit block 2 forbidscommunication of the unfixed level (Hiz: high output impedance state)transmitted from the circuit block 1, and causes a fixed level matchingthe control signal INC to be transmitted to internal circuits. Thisprevents through currents due to unfixed levels from arising in thecircuit block 2 in operation, and prevents the circuit block 2 frombeing caused to operate erroneously by any input of an unfixed level. Inother words, the circuit block 2 is enabled to realize its signalprocessing, which is its essential function.

FIG. 2 is a timing chart illustrating the operation of the circuit block3 in FIG. 1. The circuit block 3, though not illustrated in FIG. 1,generates the control signal SWC for controlling power supply to thecircuit block 1 in response to a clock signal CLK, such as a systemclock, and a standby signal STB, and the control signal INC forpreventing propagation of unfixed levels in the circuit block 2. Whenthe standby signal STB is generated, the circuit block 3 deciphers thatsignal, thereby determines the circuit block 1 to be in a standby state,and transmits the control signal INC for preventing propagation ofunfixed levels to the circuit block 2 in synchronism with the clockpulse CLK. Thus, in response to the high level of the control signalINC, the input circuit of the circuit block 2 forbids signalcommunication from the circuit block 1, and forms a fixed levelconforming to the control signal INC. After that, the control signal SWCfor power supply control varies from the high to low level insynchronism with the clock pulse CLK, the power switch in the circuitblock 1 is turned off to cut off power supply to the circuit block 1.

FIG. 3 is an overall block diagram of a semiconductor integrated circuitdevice, which is a preferred embodiment of the invention. In thisdrawing, the semiconductor integrated circuit device is shown to operateon two source voltages VCC and VDD, though this is not the only possibleconfiguration. The source voltage VCC is relatively high, such as 3.3 V,and the source voltage VDD is relatively low, such as 1.2 V, thoughagain these are not absolutely required. The relatively high sourcevoltage VCC and a ground potential VSS matching it are supplied to aninput/output (I/O) buffer and a VCC-supplied logical circuit disposed inthe peripheries of the chip. The relatively low source voltage VDD and around potential VSS matching it are supplied to the VDD-supplied logicaloperation circuits 1 and 2 and a power supply control circuit SYSC. TheVDD-supplied logical operation circuits 1 and 2 are supplied with powerswitches SW1 and SW2. Unlike them, the VCC-supplied logical operationcircuit has no such power switch, but is supplied with the sourcevoltage VCC and the ground potential VSS all the time. The power supplycontrol circuit SYSC is also supplied with the source voltage VDD andthe ground potential VSS all the time.

The VDD-supplied logical circuits 1 and 2 are configured of MOSFETs of ahigh threshold voltage HVth, a medium threshold voltage MVth and a lowthreshold voltage LVth, though this is no absolute requirement. Forinstance, a circuit to receive signals transmitted from other circuitblocks usually need not operate at very high speed, and therefore isconfigured of a MOSFET having a high threshold voltage HVth. Eachinternal circuit is configured of a combination of MOSFETs having amedium or low threshold MVth or LVth according to its speed requirement.Thus, while MOSFETs having a low threshold LVth are used on a signaltransmission path where there are many logical steps because the delaytime per logical step should be reduced, MOSFETs having a mediumthreshold voltage MVth are used on a signal transmission path where thenumber of logical steps is moderate because the delay time per logicalstep need not be so short, and MOSFETs of a high threshold voltage HVthare used on a signal transmission path where the number of logical stepsis small because the delay time per logical step can be long.

When signals are to be communicated between the VDD-supplied logicaloperation circuit 1 or 2 and the VCC-supplied logical circuit, there isprovided a micro input/output circuit μIO for level conversion toconvert VDD-supplied small amplitude signals into VCC-supplied largeamplitude signals. Since power is supplied all the time to theVCC-supplied logical circuit in this embodiment as stated above, thisconversion is used for preventing propagation of unfixed levels byutilizing the micro input/output circuit μIO when power supply to theVDD-supplied logical operation circuit 1 or 2 is cut off. For thisreason, the control signals SWC and INC formed by the power supplycontrol circuit SYSC are delivered to the respective power switches SW1and SW2 of the VDD-supplied logical operation circuits 1 and 2 and theinput circuit as indicated by dotted lines in the diagram. The controlsignal INC is also delivered to the micro input/output circuit (IO aswill be described afterwards.

FIG. 4 is a circuit diagram of an example of input circuit provided inthe micro input/output circuit of FIG. 3. This input circuit, receivinga VDD level input signal supplied from an input terminal in and suppliesfrom an output terminal output a VCC level output signal havingundergone level conversion. The input terminal in is connected to theinput terminal of an inverter circuit NV1 operating on the low sourcevoltage VDD. This input terminal in is connected to the gate of anN-channel MOSFET M2 which performs level conversion, and the outputterminal of the inverter circuit NV1 is connected to the gate of anN-channel MOSFET M1 which performs level conversion. The groundpotential of the circuit is given to the sources of these MOSFETs M1 andM2, and between their drains and the high source voltage VCC aredisposed P-channel MOSFETs M3 and M4 whose gates and drains arecross-connected. The level-converted output signal from the commonlyconnected drains of the MOSFETs M2 and M4 is supplied to one of theinput terminals of the NAND gate circuit G1. The other input terminal ofthis NAND gate circuit G1 is supplied with the control signal INC forpreventing propagation of unfixed levels.

In this embodiment, when the control signal INC is set to the high level(logic 1), the gate circuit G1 inverts the signal converted in levelfrom the VDD level to the VCC level and delivers the inverted signal. Onthe contrary, when the control signal INC is set to the low level (logic0), the output signal of the gate circuit G1 is fixed to the high level(logic 1) irrespective of the level-converted signal. In other words,the power supply to the VDD-supplied logical operation circuit whichsupplies the source voltage VDD to the inverter circuit NV1 and theinput signal to the input terminal in is cut off, with the result that,even if the level-converted signal takes on an unfixed level, such as ahigh output impedance, the output signal of the gate circuit G1 can befixed to the high level (logic 1), unaffected by the unfixed level, bysetting the control signal INC to the low level (logic 0). As a result,in the VCC-supplied logical circuit, inputting of any unfixed level canbe prevented from inviting a through current or erroneous operation.

FIG. 5 shows the configurations of the smallest units of anothersemiconductor integrated circuit device pertaining to the invention.This embodiment of the invention is a variation of what is shown in FIG.1, and its configuration differs from that of the embodiment of FIG. 1in that a response signal ACK matching the power supply control signalSWC is delivered from the circuit block 1 to the circuit block 3.Receiving this response signal ACK, the circuit block 3 generates thepower supply control signal SWC and the control signal INC forpreventing propagation of unfixed levels matching that signal SWC. Inthis drawing, these signal routes are distinguished from the routes ofordinary operational signals by being indicated in dotted lines.

FIG. 6 is a waveform chart illustrating an example of operation of thecircuit embodying the invention, shown in FIG. 5. As in theconfiguration shown in FIG. 2, the circuit block 3 is caused to generatethe control signal INC for preventing propagation of unfixed levels; theinput circuit provided in the circuit block 2 stops capturing anyunfixed level or any other input signal; after forming a fixed levelmatching the control signal INC, the power supply control signal SWC isset to the low level to turn off the power switch of the circuit block1; the source voltage VDD for instance drops, and power supply is cutoff. Therefore, as in the foregoing case, even if the output signal ofthe circuit block 1 becomes unfixed in level as a result of the powercut-off, the circuit block 2 is maintained at the fixed level.

Then, the power supply control signal SWC is raised to the high level bythe circuit block 3 to turn on the power switch of the circuit block 1to cause the source voltage VDD, for instance, to rise. The circuitblock 1 here is provided with a voltage detecting circuit, which detectsthe rise of the source voltage VDD and, when the voltage reaches a levelrequired for the operation of the circuit block 1, generates theresponse signal ACK. After having a power supply control circuit unit orthe like generate a timing margin upon receipt of this response signalACK, the circuit block 3 judges that the output level of the circuitblock 1 is not an unfixed level, and control is so effected as to enablethe signal formed by the circuit block 1 to be received by the circuitblock 2 by setting the control signal INC for preventing propagation ofunfixed levels to the low level.

FIG. 7 and FIG. 8 are block diagrams illustrating operating forms of aninput circuit for preventing the propagation of unfixed levels accordingto the invention. FIG. 7 and FIG. 8 showcases wherein there is a switchover from the upper state in which power supply is on to both thecircuit blocks 1 and 2 to the lower state in which power supply to onlythe circuit block 1 is off.

FIG. 7(A) shows a case in which a latch circuit is used as the inputcircuit. This is a state in which, when power supply to both the circuitblocks 1 and 2 is on, a signal of the high level (H) is delivered fromthe circuit block 1 to the circuit block 2. And when power supply toonly the circuit block 1 is to be turned off as indicated by an arrow,the latch circuit fixes the high level (H) with the control signal INCfor preventing propagation of unfixed levels generated before that, andoutputs that signal fixed to the high level.

FIG. 7(B) shows a case in which a logical sum type circuit is used asthe input circuit. This is a state in which, when power supply to boththe circuit blocks 1 and 2 is on, a high level/low level (H/L) isdelivered from the circuit block 1 to the circuit block 2. And whenpower supply to only the circuit block 1 is to be turned off asindicated by an arrow, a logical sum type circuit, such as a NORcircuit, fixes the low level (L) with the high level (logic 1) of thecontrol signal INC for preventing propagation of unfixed levelsgenerated before that, and outputs that signal fixed to the low level.Where an OR circuit, another logical sum type circuit, is used as theinput circuit, the high level (H) of the signal is fixed with the highlevel (logic 1) of the control signal INC, and outputs that signal fixedto the high level.

FIG. 8(A) shows another case wherein a latch circuit is used as theinput circuit. This is a state in which, when power supply to both thecircuit blocks 1 and 2 is on, a signal of the high level (L) isdelivered from the circuit block 1 to the circuit block 2. And whenpower supply to only the circuit block 1 is to be turned off asindicated by an arrow, the latch circuit fixes the high level (L) withthe control signal INC for preventing propagation of unfixed levelsgenerated before that, and outputs that signal fixed to the high level.

FIG. 8(B) shows a case in which a logical product type circuit is usedas the input circuit. This is a state in which, when power supply toboth the circuit blocks 1 and 2 is on, a high level/low level (H/L) isdelivered from the circuit block 1 to the circuit block 2. And whenpower supply to only the circuit block 1 is to be turned off asindicated by an arrow, a logical product type circuit, such as a NANDcircuit, fixes the high level (H) with the low level (logic 0) of thecontrol signal INC for preventing propagation of unfixed levelsgenerated before that, and outputs that signal fixed to the high level.Where an AND circuit, another logical product type circuit, is used asthe input circuit, the low level (L) of the signal is fixed with the lowlevel (logic 0) of the control signal INC, and outputs that signal fixedto the low level.

FIG. 9 is a timing chart illustrating an example of standby shiftingsequence of a specific circuit block in a semiconductor integratedcircuit device embodying the invention. In a device managing the wholesystem mounted with this semiconductor integrated circuit devicepertaining to the invention, for instance a central processing unit(CPU) or the like for executing signal processing of the system inaccordance with a program, when the execution of the program generates astandby control signal to instruct a specific circuit block to shift toa standby state, a power supply instruction signal is entered into thissemiconductor integrated circuit device pertaining to the invention thepower supply control circuit SYSC shown in the circuit block 3 raisesthe input control signal to the high level, and a fixed level matchingthe input control signal is formed for the input circuit, which isdisposed in the circuit block to which power supply is to be turned onand receives a signal from the circuit block to which power supply is tobe turned off.

After an operation to forbid propagation of signals of unfixed level isexecuted by the high level of such an input control signal, aninstruction to cut off power supply by setting the power supply controlsignal to the low level is given from the power supply control circuitSYSC to the circuit block to which power supply is to be turned off. Inthe circuit block to which power supply cut-off has been instructed, apower supply cut-off sequence in which the power switch is turned off tomatch the low level of the power supply control signal is executed. Forthis reason, the circuit block to which power supply is to be turned offis provided with a circuit which, as will be described afterwards, issupplied with power all the time and performs control turn on and offpower supply. This power supply cut-off sequence is communicated to thepower supply control circuit SYSC by the low level of the power supplyacknowledge signal. And in the power supply control circuit SYSC, apower supply cut-off confirm signal is communicated to, among others,the CPU having issue the standby control signal.

FIG. 10 is a timing chart illustrating an example of return from standbysequence of the specific circuit block in the semiconductor integratedcircuit device pertaining to the invention. As in the foregoing case,when standby control signal to instruct the specific circuit block toreturn from a standby state is generated by the execution of the programby the central processing unit (CPU) or the like managing the wholesystem, a power supply instruction signal is inputted to thissemiconductor integrated circuit device pertaining to the invention, aninstruction to turn on power supply is given by delivering a powersupply control signal set to the high level from the power supplycontrol circuit SYSC shown as the circuit block 3 to the circuit blockto which power supply is to be turned on. In the circuit block to whichpower supply has been instructed, a power supply duration by which thepower switch is to be turned on to match the high level of the powersupply control signal is executed by the circuit described above. And,after waiting for a certain period which power turning-on is completed,the input control signal is reduced to the low level, and the inputcircuit performs an operation capture into the circuit block 2 a signalfrom the circuit block to which power supply has been turned on. Then,though not shown, the power supply acknowledge signal is also deliveredto the power supply control circuit SYSC to inform the CPU or the like,which has issued the standby control signal, of the control of thegeneration of the input control signal and a power supply turn-onconfirm signal.

FIG. 11 is a schematic block diagram of a whole system pertaining to theinvention corresponding to FIG. 9 and FIG. 10. An instruction to place aspecific circuit block in a standby state is given to the circuit block3 with signals A and B from a device managing the standby mode,typically a CPU. The module to manage the standby mode is not limited tothe CPU, but may be any appropriate module. The signals A and Bcorrespond to, for instance the standby control signal and the powersupply instruction signal shown in FIG. 9 and FIG. 10 above. The circuitblock 3 forms the power supply control signal SWC correspondingly tosuch signals A and B, and delivers them to a power switch controllerPSWC. The power switch controller PSWC, as will be described afterwards,is a circuit appended to the circuit block 1 placed in the standbystate, and returns to the circuit block 3 a control signal forperforming on/off control of the power switch provided for the circuitblock 1 and the response signal ACK matching the power supply controlsignal SWC. Whereas power switch controller PSWC is contained in thecircuit block 1 in FIG. 1, FIG. 5 and other drawings above, since avoltage is constantly supplied to it, it is shown as a separate circuitblock from the circuit block 1 in FIG. 11 to make clear this constantvoltage supply.

Signals formed in the circuit block 1 are communicated to the circuitblock 2. The circuit block 2 is provided with the input circuit forreceiving signals delivered from the circuit block 1, and is controlledwith the control signal INC for preventing propagation of unfixed levelsgenerated in relation to the power supply control signal SWC. Thus,before power supply to the circuit block 1 is cut off with the powersupply control signal SWC, the level of the signal to be delivered tothe circuit block 2 is fixed as stated above with such control signalINC to prevent in advance the unfixed level (Hiz) accompanying the powersupply cut-off from being communicated. Between the circuit block 3 andthe CPU and the like, signals C, D, E and so forth are exchanged. Thesesignals C, D and E are signals required by the CPU or the like executingthe program for reliably controlling the operation of the whole system,such as a power supply cut-off confirm signal, a return from standbysignal or a standby release signal.

FIG. 12 is a schematic block diagram of one example of semiconductorintegrated circuit device pertaining to the invention. This is avariation of the embodiment shown in FIG. 1 above, with a circuit block4 being added. Although this circuit block 4 delivers signals to thecircuit block 1 and the circuit block 2, neither of the two circuitblocks 1 and 2 delivers signals to it. To the circuit block 1, signalsare delivered only from the circuit block 4. To the circuit block 2,signals are delivered from both the circuit blocks 1 and 4. An inputcircuit or circuits are provided to match signals delivered in this wayto each block. Thus, the circuit block 1 is provided with one inputcircuit to match signals from the circuit block 4, and the circuit block2 is provided with two input circuits to match signals from the circuitblocks 1 and 4.

Therefore, the circuit block 3 generates two kinds of signals forpreventing propagation of unfixed levels, the control signals INC1 andINC4, to match power supply cut-off to the circuit blocks 1 and 4. Thus,when power supply to the circuit block 4 is to be turned off,correspondingly the control signal INC4 is generated to control theinput circuits of the circuit blocks 1 and 2 to prevent any unfixedlevel from the circuit block 4. When power supply to the circuit block 1is to be turned off, correspondingly the control signal INC1 isgenerated to control the input circuit of the circuit block 2 to preventany unfixed level from the circuit block 1. As the circuit block 2delivers signal to neither of the circuit blocks 1 nor 4, there is noneed to generate a matching control signal INC for preventingpropagation of unfixed levels. Further, even the circuit block 4, whichdoes receive signals from other circuit blocks land 2 as illustrated inthe drawing, requires no input circuit for preventing propagation ofunfixed levels on condition that power supply to it is off whenever thatto other circuit blocks 1 and 2 is off.

FIG. 13 is a schematic block diagram of another semiconductor integratedcircuit device pertaining to the invention. This is a variation of theembodiment shown in FIG. 12 above, in which signals are delivered to theadditional circuit block 4 from the circuit block 1. Matching suchsignals delivered from the circuit block 1, an input circuit is disposedin the circuit block 4. In this embodiment, the relationship between thecircuit blocks 1 and 4 is different from that in FIG. 12 above, andpower supply to the circuit block 1 is allowed to be turned off whenthat to the circuit block 4 is on. Therefore in the circuit block 3, inthe same way as described above, when power supply to the circuit block1 is to be turned off, correspondingly the control signal INC1 isgenerated to control the input circuits of the circuit blocks 2 and 4 toprevent any such unfixed level from the circuit block 1.

FIG. 14 is a schematic block diagram of still another semiconductorintegrated circuit device pertaining to the invention. This is avariation of the embodiment shown in FIG. 12 above, in which signals aredelivered to the additional circuit block 4 from not only the circuitblock 1 but also the circuit block 2. Also, the circuit block 2 deliverssignals to the circuit block 1. Furthermore, the circuit block 3 isprovided with a logical circuit which in its operation receives signalsfrom the circuit blocks 1, 2 and 4 in addition to the aforementionedpower supply control circuit SYSC. Viewed the other way around, if thereis a specific circuit block 3 which can keep the power supply controlcircuit SYSC supplied with power all the time, it will be incorporatedthere. Such a circuit block 3 is provided with three input circuits tomatch signals from the circuit blocks 1, 2 and 4.

Therefore, the power supply control circuit SYSC of the circuit block 3generates three kinds of signals for preventing propagation of unfixedlevels, the control signals INC1, INC2 and INC4, to match power supplycut-off to the circuit blocks 1, 2 and 4. When power supply to thecircuit block 1 is to be turned off, correspondingly the control signalINC1 is generated to control the input circuits of the circuit blocks 2,3 and 4 to prevent any such unfixed level from the circuit block 1. Whenpower supply to the circuit block 2 is to be turned off, correspondinglythe control signal INC2 is generated to control the input circuits ofthe circuit blocks 1, 3 and 4 to prevent any such unfixed level from thecircuit block 2. And when the circuit block 4 is to be turned off,correspondingly the control signal INC4 is generated to control theinput circuits of the circuit block 1, 2 and 3 to prevent any suchunfixed level from the circuit block 4. In this manner, power supply toany of the circuit blocks 1, 2 and 4, but not the circuit block 3, canbe turned off as desired, and correspondingly the control signals INC1,INC2 and/or INC4 are generated in advance.

FIG. 15 is a schematic layout of another example of semiconductorintegrated circuit device pertaining to the invention. The layout inthis drawing centers on power supply lines formed in the semiconductorintegrated circuit device pertaining to the invention. The power supplylines comprise a pair of a source voltage line and the ground wire ofthe circuit, and the latter is hatched to make the wiring layout moreeasily perceivable.

The semiconductor integrated circuit device of this embodiment isdesigned to operate on two kinds of source voltages, vcc and vdd. Thesource voltages vcc are relatively high, such as 3.3 V, and the sourcevoltages vdd are relatively low, such as 1.2 V, though these are notabsolutely required. The relatively high source voltages vcc have asource voltage vccaa for analog and logical units, a source voltage vccqfor input/output circuits and a source voltage vcci for internalcircuits. Respectively matching these source voltages vccaa, vccq andvcci, there are provided circuit ground potentials vssaa, vssq and vssi.The power supply lines expressed in bold wiring lines along the outercircumference of the semiconductor chip are bisected into one for analogcircuits and the other for digital circuits; the source voltages vccaaand vccq are arranged outside, and inside the respective ones of themare arranged circuit ground vssas and vssq. As vcc-supplied internalcircuits each having a specific circuit function, there are avcc-supplied logical unit and an analog logical unit, and power supplylines represented by fine wiring lines surround each. The power supplylines surrounding the vcc-supplied logical unit are connected to powersupply pads vcci and vssi. The power supply lines surrounding the analoglogical unit, together with the bold power supply lines, are connectedto power supply pads (PAD) vccaa and vssaa.

There are disposed two kinds of power supply lines vdd and vss,including what are represented by thin ring-shaped ones along the insideof the power supply line represented by bold wiring lines and what matchthe internal circuits to be described afterwards. The vdd-power supplylines arranged in a ring shape are used for supplying the operatingvoltage of a level converting circuit for converting vdd-internalsignals into large amplitude signals, such as the vcc signals in aninput/output interface and operating voltages including those for thevdd-supplied internal circuits operating all the time, such as micro ioexchanging signals among a vdd-supplied logical unit 1, a vdd-suppliedlogical unit 2 and a vcc-supplied logical unit. The vdd-suppliedinternal circuits include the vdd-supplied logical unit 1 and thevdd-supplied logical unit 2. Surrounding these circuit blocks, powersupply lines represented by thin wiring lines are disposed. Thevdd-supplied logical unit 2 is provided with independent power supplypads (PAD), such as vddi and vssi, for the purpose of noise separationbetween the vdd-supplied logical unit 1 and the internal circuitsoperating on the ring-shaped power supply lines.

Matching the power supply lines, power supply pads (PAD) vcc and vss,vdd and vss, vccq and vssq, vccaa and vssaa are disposed, each in aplurality of sets as required. Among other pads (PAD) illustrated asrepresentative ones, aio are intended for inputting/outputting analogsignals, and vdd-dio are intended for direct digitalinputting/outputting between the vdd-supplied logical unit 1 and thevdd-supplied logical unit 2. Illustration of vcc-supplied pads forsignal inputting/outputting is dispensed with in this drawing. Therectangular blocks shown correspondingly to the pads constituteinput/output interface circuits. Signal input/output pads matching theinput/output interfaces are represented by such typical examples as thepads dio and aio. In particular, input/output pads for digital signalsare disposed in a large number, along with power supply pads,surrounding the outer circumference of the semiconductor chip.

In this embodiment, the internal circuit blocks of the vdd-suppliedlogical unit 1 and the vdd-supplied logical unit 2 are provided with afunction to enter a power saving mode when no operation is done eventhough power supply is on. In order to realize this power saving mode,power switches PSW are disposed underneath the power supply lines formedto surround the internal circuits, and power switch control circuitsPSWC are arranged underneath the corners of the power supply lines.Furthermore, power supply main lines (vcc and vss, vdd and vss, vccq andvssq, vccaa and vssaa) formed to surround the respectively matchingcircuits in order to reduce the impedances of the power supply lines tobe described afterwards among other purposes are formed of relativelythick aluminum pad wires ALP, formed in the same process as the bondingpads.

FIG. 16 is a layout of one example of power supply lines matching thevdd-supplied logical unit 2 in FIG. 15. In this embodiment, the powersupply lines are configured in a cell form. The variety of cells, thoughnot limited, can be prepared in four types, A through D, broadlyclassified. In the directions of letters A through D, the cells Cconstitute power supply lines extending in the longitudinal direction.The cells B constitute power supply lines extending in the lateraldirection. The cells A constitute corners formed by the longitudinal andlateral power supply lines. The cells B include standard cells andmini-cells B for length adjustment, though this differentiation is notabsolutely necessary.

The cells E constitute power supply lines extending in the longitudinaldirection above the part where the vdd-supplied logical unit 2 isformed, and connect the opposite cells B. These cells E are used forconfiguring a power supply mesh to be described afterwards. The cells D,which are internal linking cells, extend in the lateral direction fromthe power supply lines extending in the longitudinal direction, and areused for linking with the internal power supply lines of the internalcircuits. Circuit elements constituting the power switch elements andpower switch control circuits are arranged underneath the cells A, B andC out of these cells A through E. Unlike them, the cells E are only forpower supply lines. The cells D are provided with under-layer wiring forlinking with internal power supply lines.

FIG. 17 is a schematic layout of one example of lower part of the powersupply line matching the vdd-supplied logical unit 1 in FIG. 15. In thisembodiment, the relationship between the cells C and the cells A ismainly illustrated. The cells C are provided with switches. Each ofthese switches is connected at one end to the ground wire vssi of thecircuit out of the source voltage lines vddi and vssi disposed above andat the other end to a ground wire for supplying the ground potential ofthe circuit to the internal logic area, though these connections are notthe only possible ones. In the internal logic area, there is a laterallywide well area in which P-channel MOSFETs and N-channel MOSFETsconstituting CMOS logical circuits like gate arrays are formed, thoughthis is not the only possible arrangement, and switches are disposedcorrespondingly along this well area. Along the P-type well in which theN-channel MOSFETs are formed, the ground wires vss of the internalcircuits are arranged in the lateral direction. On the other hand, alongthe N-type well in which P-channel MOSFETs are formed, power supplylines vdd are arranged in the lateral direction. In this drawing, theblocks dividing the internal logic area longitudinally and laterallymatch the respective circuit areas in which the N-channel MOSFETs andthe P-channel MOSFETs are formed.

In the cell A arranged at the top left corner, there is disposed a powersupply SW controller (power switch control circuit PSWC) for the on/offcontrol of the switches provided in the cells C. Switch control signalsformed by this power supply SW controller are delivered to individualswitches via the power supply SW control signal lines indicated bydotted lines in the drawing. In this drawing, the power supply SWcontrol signal lines for controlling the power SWs (switches) disposedin the cells C arranged to the left of the internal logic area deliversignals to the switches in the cells C by utilizing wiring areasdisposed in these cells C.

The power supply SW control signal lines for controlling the powersupply SWs disposed in the cells C arranged to the right of the internallogic area deliver signals to the switches in the cells C arranged tothe right by utilizing wiring areas disposed in the cells B and wiringareas disposed in the cells A. Since these switches are intended forcontrolling power supply to the internal circuits as stated above, nosuch switches are needed in the corners. Therefore, by arranging thepower supply SW controller (power switch control circuit PSWC), thecircuit formation area underneath the power supply lines is effectivelyutilized.

Out of the switches disposed in the cells C as described above, thosefor supplying the ground potential of the circuit are providedcorrespondingly to internal ground wires matching the laterally wideP-well area in which N-channel MOSFETs are formed. Therefore, in theunoccupied areas of the cells C matching the N-type well area in whichP-channel MOSFETs are formed, capacitors can be disposed for use instabilizing power supply. Similarly, capacitors can also be disposed inthe cells B underneath the power supply lines.

FIG. 18 is a circuit diagram illustrating the relationship among thepower supply SW controller (PSWC), the power supply SW and the internallogic in FIG. 17. An inverter circuit shown as representing the internallogic works on the operating voltage transmitted via the power supplyline vdd and the internal ground wire vssm. On the power supply line vddof the internal logic, the source voltage supplied from theaforementioned external terminal is constantly delivered via the padsand wiring routes. The internal ground wire vssm is connected to theground wire vss formed to surround the internal circuits via theN-channel MOSFETs Q1 and Q2 as power supply SWs (switches) illustratedas being representative. The gates g of the MOSFETs as the plurality ofswitches provided to match the cells C are commonly supplied with thepower supply SW control signal.

The power supply SW controller (PSWC) generates switch control signalsfor the MOSFETs Q1 and Q2 and the like in response to a control signalreq. If the MOSFETs Q1 and Q2 are switched over from the off state tothe on state at high speed in the internal logic, currents will flowsimultaneously in the inverter circuit, logical gate circuits and thelike in the internal logic on account of the input signal being unfixedand other reason, giving rise to large noise in the source voltage vddthe ground potential vss of the circuit or imposing the burden of largeinstantaneous current supply on the power supply unit of the system. Inview of this problem, in this embodiment, power supply SW controlsignals to drive the MOSFETs Q1 and Q2 in two separate stages aregenerated by two driving circuits C1drv and C2drv, output circuits C1and C2 thereby caused to generate output signals, a decision circuit C3for determining the level of the power supply SW control signals and atimer circuit Timer.

When the control signal req instructs an action to turn on power supply,the driving circuit C1drv in response raises the gate voltages of theMOSFETs Q1 and Q2 as the power switches through the output circuit C1.The output circuit C1 is formed of a MOSFET whose current supplycapacity is small, and the connection of the gates g of the MOSFETs Q1and Q2 and so forth as a large number of power switches results in agradual rise in the level of the power supply SW control signal linehaving a large load capacity. The MOSFETs Q1 and Q2 and so forth aspower switches are thereby so controlled as to let flow relatively smallcurrents when their gate voltage reaches or surpasses the thresholdvoltage. It is thereby made possible to prevent the aforementionedproblem of giving rise to large noise in the source voltage vdd and theground potential vss of the circuit or imposing the burden of largeinstantaneous current supply on the power supply unit on account of theinput signal being unfixed in the inverter circuit or the logical gatecircuits of the internal logic. To add, as the occurrence of noise islikely to adversely affect other logical circuits, interface circuitsand analog circuits in operation, this is a problem that has to be takeninto consideration where the system is to be equipped with a function toshift to a power saving mode by cutting off power supply to some circuitwhen no action is to be done on that circuit.

The timer circuit Timer actuates the output circuit C2 via the drivingcircuit C2drv when the voltage decision circuit C3 having hysteresischaracteristics determines that the power supply SW control signal linehas reached or surpassed a certain level. The output circuit C2 isformed of a MOSFET whose current supply capacity is large, and raisesthe level of the gates g of the MOSFETs Q1 and Q2 at high speed as alarge number of power switches to the source voltage vdd. This placesthe vdd-internal logic in an operating state. The timer circuit Timersupplies with a delay in time a signal ack indicating the validity ofthe operation of the internal logic and informs other circuits of thisvalidity. A signal cds/cdr, which is a signal for controlling the microio, is used to limit the signal output conveyed to the micro io, forinstance, until the signal of the internal logic is found valid. Thesignal ack can be used as the response signal ACK.

FIG. 19 is a schematic layout of one example of cell C. In FIG. 19, thepower supply lines of the top layer and an element-formed partunderneath them are shown one over the other. The lower part of thedrawing shows the power supply lines of the top layer, wherein vdd andvss are paired. In this embodiment the power supply lines vdd and vssare formed of relatively thick aluminum layers (ALP), formed in the sameprocess as the bonding pads. The core side is the side of the internallogic area, and the pad metal wiring on the core side can be varied tomatch the potentials to be connected into, such as vdd, vss and vssm.

The upper part of the drawing shows the element-formed part, wherein aplurality of gate electrodes extending in the lateral direction aredisposed, arrayed in the longitudinal direction. Diffusion layersconstituting sources and drains are formed, sandwiched between the gateelectrodes. The diffusion layers sandwiched between the two gateelectrodes constitute the common sources or drains of the MOSFETs havingthe two gate electrodes, and the sources and drains are alternatelyarranged with the gates between them. On the I/O side (right-hand side),every other diffusion layer is made a common source and connected to thepower supply line vss. On the core side, every other one of thedifferent diffusion layers from the above is made a common drain andconnected to the vssm metal wiring, which is the ground wiring of theinternal logic circuit. On the right hand side in the cell frame, aplurality of wiring layers extending in the longitudinal direction areprovided to be used as wiring between the corner control circuits and aswiring for conveying power supply SW control signals.

FIG. 20 shows a schematic structural section of one example of powersupply line of the semiconductor integrated circuit device pertaining tothe invention. In FIG. 20, a supply route of the source voltage vdd isillustrated as a representative of the routing. Thick bonding padsconsisting of aluminum or the like are connected to a copper wiringlayer. On one hand it is connected to a power supply main line ALPconsisting of aluminum or the like and formed in the upper layer, and onthe other hand it is connected via the wiring layer and contactsdisposed in the lower layer to the N-type well area Nwin which P-channelMOSFETs are formed. This configuration places in a parallel relationshipthe power supply main line consisting of the lower wiring layer ofcopper and the upper wiring layer of aluminum. This causes the currentsneeded for the operation of the internal logic to flow divided betweenthose two power supply routes, more of them flowing on the main lineside to enable the impedance of the power supply line low. As a result,unevenness or variations of the source voltage in individual logicalcircuits while the internal logic is operating can be restrained. Sinceunevenness or variations of the source voltage greatly affects circuitoperation when the internal logic is operating at a low voltage, such asthe aforementioned 1.2 V (or even below), this embodiment can beexpected to enable the internal logic circuits to operate stably. Thisalso holds true of the ground wiring which provides the groundpotentials of the circuits.

FIG. 21 is a circuit diagram of one example of step-down power supplycircuit to be mounted on the semiconductor integrated circuit devicepertaining to the invention. In this embodiment, in the semiconductorintegrated circuit device shown in FIG. 3 or FIG. 15 above, besides alow voltage VDD supplied from an external terminal, a high voltage VCCis supplied from outside and reduced to VDD by the step-down powersupply circuit illustrated therein and delivered to internal circuits.Further, a power switch function is added to this voltage step-downcircuit.

The collectors and bases of the transistors Q1 and Q2 and connected tothe ground potential points of the circuit. The size (emitter area) ofthe transistor Q2 is made N times as large as that of the transistor Q1and the current flowing to the emitter of the transistor Q1 is N timesas dense as that flowing to the emitter of the transistor Q2 to keepconstant the voltage difference between the base and the emittermatching the silicon band gap. One end of a resistor R6 is connected tothe emitter of the transistor Q2, and control is so performed with adifferential amplifier to equalize the potential of the node N1 of theemitter of the transistor Q1 and that of the node N2 at the other end ofthe resistor R6.

Thus the voltages of the nodes N1 and N2 are entered into thedifferential amplifier, its output voltage VRO is fed back to the nodesN1 and N2 via the resistors R4 and R5, a constant voltage matching thesilicon band gap is supplied to the resistor R6, a constant current islet flow to the resistor R6, and control is so effected as to make theoutput voltage VRO a constant voltage (reference voltage) matching thesilicon band gap by letting this constant current to the resistor R5.The resistors R5 and R4, by utilizing their positive temperaturecharacteristics, compensate for the negative temperature characteristicsof the base-emitter voltages of the transistors Q1 and Q2. The referencevoltage VRO is about 1.1 V.

The differential amplifier is configured of the following circuitelements. P-channel type MOSFETs MP6 and MP7 are connected in adifferential form. The gates of the differential MOSFETs MP6 and MP7 areconnected to the nodes N1 and N2. AP-channel MOSFET MP4, constituting acurrent source, is disposed between the common source of thedifferential MOSFETs MP6 and MP7 and the source voltage VDD or thecircuit. Diode-form N-channel MOSFETs MN4 and MN5 are disposed betweenthe drains of the differential MOSFETs MP6 and MP7 and the groundpotential of the circuit. The diode-form N-channel MOSFETs MP4 and MP5are provided with N-channel MOSFETs MN3 and MN6 in the current mirrorform. This causes a current matching the drain current of the MOSFET MP6to be supplied from the drain of the MOSFET MN3.

The drain current of the MOSFET MN3 is supplied via a current mirrorcircuit consisting of P-channel type MOSFETs MP2 and MP3. The outputcurrent is supplied to the drain of the MOSFET MN6. As a result, adifferential current between the drain currents of the differentialMOSFETs MP6 and MP7 is caused to flow to the commonly connected drain ofthe MOSFETs MP3 and MN6. The common connection point of the MOSFETs MP3and MN6 is connected to the gate of a P-channel MOSFET Q8. The drain ofthis MOSFET MP8 is connected to the resistors R4 and R5 to constitutethe output voltage VRO.

A resistor R1 and a diode-form N-channel MOSFET MN1 are connectedbetween the source voltage VDD and the ground potential of the circuit.An N-channel MOSFET MN2 is connected to this MOSFET MN1 in the currentmirror form. A diode-form P-channel MOSFET MP1 is disposed between thedrain and source voltage of this MOSFET MN2, and the connection of thisMOSFET MP1 and the MOSFET MP4 in the current mirror form causes acurrent matching a current formed by the resistor R1 to serve as thebias current for the differential MOSFETs MP6 and MP7.

The transistors Q1 and Q2 are configured by using the CMOS process. Theymay be lateral transistors each having N-type source and drain regionsconstituting an N-channel MOSFET, formed by the CMOS process, as itscollector and emitter and having a P-well base; or vertical transistorseach having an N+ region constituting the source and drain regions of anN-channel MOSFET as its emitter, having the P-type well where it isformed as its base, and an N-type deep well for separating the P-typefrom a P-type substrate (PSUB) as its collector. In this way, a highlyaccurate reference voltage hardly affected by the offset of the CMOSdifferential amplifier circuit is obtained, and it is made possible toform the circuit by the CMOS process.

The reference voltage VRO is supplied, though not absolutely required,to the input terminal (−) of a differential amplifier circuit OP. Theoutput signal of this differential amplifier circuit OP is communicatedto the gate of a P-channel output MOSFET MP10. A stepped-down outputvoltage VDD is supplied from the drain of this P-channel MOSFET MP10.This output voltage VDD is divided by feedback resistors R7 and R8disposed between the drain and the ground potential of the circuit, andthe resultant divided voltages are inputted to the feedback terminal (+)of the differential amplifier circuit OP to form an output voltage VDDresulting from the amplification of the reference voltage VROcorrespondingly to the ratio of voltage division.

In this embodiment, in order to add a switching function, a controlsignal/POFF is supplied to the gate of an N-channel MOSFET MN7 to whichthe operating current of the differential amplifier circuit OP is letflow. Further, a P-channel MOSFET MP9 is disposed between the gate ofthe P-channel output MOSFET MP10 and the source voltage VCC, and thecontrol signal/POFF is supplied to the gate. One silicon band gapcircuit, though not necessarily limited to one, to generate thereference voltage VRO is disposed in the semiconductor integratedcircuit device, and the differential amplifier circuit OP and the outputMOSFET MP10 are provided corresponding to the circuit blocks 1, 2 and 4having the power turning-off function.

When the source voltage VDD is to be supplied to a specific circuitblock, the control signal/POFF is raised to the high level. The MOSFETMN7 is turned on, and an operating current islet flow to thedifferential amplifier circuit OP. On this occasion, the P-channelMOSFET MP9 is turned off. When the supply of the source voltage VDD to aspecific circuit block is to be cut off, the control signal/POFF islowered to the low level. This causes the MOSFET MN7 to be turned off,and the differential amplifier circuit OP is placed in a non-operatingstate. Then P-channel MOSFET MP9 is in an on state and the MOSFET MP10securely turned off to cut off the source voltage VDD.

FIG. 22 is a circuit diagram of another example of step-down powersupply circuit to be mounted on the semiconductor integrated circuitdevice pertaining to the invention. This embodiment has a configurationin which, besides the configuration of the semiconductor integratedcircuit device shown FIG. 3 or FIG. 15 wherein the low voltage VDD issupplied from the external terminal, a high voltage VCC is supplied fromoutside and reduced to VDD by the step-down power supply circuitillustrated therein and delivered to internal circuits. Further, a powerswitch function is added to this voltage step-down circuit. The powerswitch in this embodiment is not to cut off the source voltage VDD as inthe foregoing embodiments, but is reduced to or below the lower voltagelimit of the internal circuits.

Thus, a bias current is regularly supplied to the differential amplifiercircuit OP by the N-channel MOSFET MN7. A P-channel MOSFET MP11 toshort-circuit the two ends of the voltage dividing resistor R7 isdisposed, though not absolutely required, to supply the aforementionedcontrol signal/POFF to its gate. In this configuration, the reduction ofthe control signal/POFF to the low level causes the two ends of theresistor R7 to be short-circuited to achieve 100% feedback of the outputvoltage VDD for operation as a voltage follower circuit. This reducesthe source voltage VDD to a voltage matching the reference voltage VRO.The source-voltage of the logical circuits is thereby reduced to orbelow the lower limit of the operating voltage, and this drop in voltagecan help reduce the flowing leak current. As the operation of thelogical circuits at or below the lower limit of the voltage may inviteunfixed levels, there is provided an input circuit for preventing thepropagation of unfixed levels as in the foregoing embodiments.

This power supply cut-off system enable a device having storagecircuits, such as memories or registers, to retain the storedinformation while reducing the leak current from power supply. Forstatic memory cells, registers using flip-flop circuits or latchcircuits, if the purpose is simply to hold stored information, abouthalf of that lower limit operation would suffice. Then, by significantlyreducing the source voltage to a voltage level which meets theinformation holding purpose alone, the leak current can be reduced fromcircuit blocks to which power supply cannot be turned off as statedabove. Where the reference voltage VRO is outputted as it is as in theembodiment shown in FIG. 22, the voltage cannot be reduced to around 1.1V. Then, it is also possible to dispose a voltage dividing circuit onthe input side of the differential amplifier circuit OP2 and divide thevoltage VRO itself to reduce the source voltage VDD to the desired lowlevel.

Referring to FIG. 21 and FIG. 22 above, instead of directly using theoutput voltage VDD of the MOSFET MP10 as the operating voltage for thecircuit blocks, it can be used as the source voltage for the circuitblocks by using an output buffer of a voltage follower type. In thiscase, where a switching function is to be added as in the embodiment ofFIG. 21, a power-off state can be forcibly achieved by cutting of theoperating current of the output buffer and short-circuiting the gate andsource of the output MOSFET. In this case, the operating current of thedifferential amplifier OP can also be cut off. Where the samestepped-down voltage VDD is to be used in a plurality of circuit blocks,the differential amplifier can be used in common, with an output bufferprovided for each block. Where the output voltage is to be brought downto the lower limit of the operating voltage as in the configuration ofFIG. 22 above, a silicon band gap circuit can be used in common, witheach circuit block provided with an amplifier circuit having theaforementioned level switching function and an output circuit.

FIG. 23 is an overall block diagram of another example of semiconductorintegrated circuit device pertaining to the invention. This embodimentrepresents a conceptual configuration of the invention as applied to,for instance, an information processing device, in particular a systemLSI (or microprocessor; the same applies hereinafter).

In the system LSI of this embodiment, each circuit block has a powerswitch PSW or VGC. The individual circuit block may be a centralprocessing unit (CPU), peripheral circuit modules IP1 and IP2 or a clockgenerator circuit CPG, to each of which power supply is turned on andoff with a power switch PSW. Other available circuit blocks includeinternal memories URAM and backup registers BUREG, each reducing theleak current while keeping the operation to hold stored information witha power switch VGC against the voltage drop as shown in FIG. 22. Powersupply to a standby control circuit STBYC is on all the time, matchesthe circuit block 3 as in 14 above, and is provided with the powersupply control circuit SYSC.

The CPU controls the system LSI as a whole. The peripheral circuitmodule IP1, though not limited to this function, is a peripheral circuitmodule which is not required when the CPU for an MPEG accelerator or thelike fetches an instruction. The peripheral circuit module IP2, whichmay be a bus state controller or the like, is a peripheral circuitmodule which is required when the CPU fetches an instruction though notlimited to this function. To the system bus BUS, various circuit modulesincluding the CPU are connected, and includes a data bus and an addressthough not shown. The clock generator circuit CPG, receiving a clocksignal RCLK, generates an internal clock signal ICLK. The internal clocksignal ICLK is supplied to various circuit modules, and the system LSIoperates in accordance with the internal clock signal ICLK. The URAM, alarge-capacity internal memory, holds necessary information includingdata currently being processed. The backup register BUREG is used, whenin the standby mode, for holding the values of register REG included inthe peripheral circuit modules IP1 and IP2.

When a given program is to be executed by the system LSI, if there is acircuit block placed in the standby state, an instruction will be givento cut off power supply to or reduce the voltage for this circuit block.In advance of instructing a power supply cut-off or a voltage reduction,the control signal INC for preventing propagation of unfixed levels isgenerated and deliver to circuit blocks to which power supply is on.This serves to reduce the leak current in the circuit block to whichpower supply is turned off, and the circuits to which power supply is onand which are used for executing the program can perform, whilepreventing any through current from being generated by the input of anyunfixed level, their signal processing operation matching the programwithout committing errors due to any unfixed level from the circuitblock to which power supply is off. Further, when power supply to theCPU or peripheral circuit modules IP1 and IP2 is to be turned off,necessary internal information therein is saved into the. The URAM orthe backup register BUREG holding such saved information can also beplaced in the standby state with a voltage drop as described above it isno longer accessed.

Although the invention made by the present inventors has been hithertodescribed in specific terms with reference to some of the embodimentsthereof, the invention is not confined to these embodiments, but variousmodifications are possible without deviating from its true spirit andscope. For instance, power switches can be disposed on the sourcevoltage side of the circuit instead of the ground potential side asdescribed above. Propagation of unfixed levels can as well be preventedby, instead of providing the micro I/O circuit with a gate circuit as inthe embodiment shown in FIG. 4, providing the VCC-supplied logicalcircuit with an input circuit for preventing the propagation of unfixedlevels as stated above. The circuit for preventing the propagation ofunfixed levels can be, instead of using the latch circuit or logicalgate circuits as described above, may forbid transmission of any unfixedlevel with a transmission gate MOSFET and providing a pull-up orpull-down MOSFET on the part of the signal-receiving circuit block. Forinstance, by using an N-channel MOSFET as the transmission gate MOSFETand the P-channel MOSFET as pull-up means, it is made possible to supplythe control signal INC for preventing propagation of unfixed levels tothe gate electrodes of the two MOSFETs. The invention can be extensivelyutilized in semiconductor integrated circuit devices each having aplurality of functional blocks such as microcomputers or system LSI.

1. A semiconductor integrated circuit device comprising: a first circuitblock; a second circuit block; and a third circuit block, wherein thefirst circuit block has a first power supply state in which theoperation of internal circuits thereof is guaranteed in accordance withan instruction from the third circuit block and a second power supplystate in which the operation of the internal circuits thereof is notguaranteed, wherein the second circuit block has an input unit whichreceives signals supplied from the first circuit block, and wherein theinput unit of the second circuit block has an input circuit which, inaccordance with a control signal which was responded to when the secondpower supply state was instructed by the third circuit block to thefirst circuit block, causes a specific signal level to be maintained incompliance with the operating voltage of the second circuit blockirrespective of the signal supplied from the first circuit block.
 2. Thesemiconductor integrated circuit device according to claim 1, whereinthe second circuit block has a first power supply state in which theoperation of internal circuits thereof is guaranteed in accordance withan instruction from the third circuit block and a second power supplystate in which the operation of the internal circuits thereof is notguaranteed, wherein the first circuit block has an input unit whichreceives signals supplied from the second circuit block, and wherein theinput unit of the first circuit block has an input circuit which, inaccordance with the control signal which was responded to when thesecond power supply state was instructed by the third circuit block tothe second circuit block, causes a specific signal level to bemaintained in compliance with the operating voltage of the first circuitblock irrespective of the signal supplied from the second circuit block.3. The semiconductor integrated circuit device according to claim 2further comprising: a fourth circuit block having a first power supplystate in which the operation of internal circuits thereof is guaranteedin accordance with an instruction from the third circuit block and asecond power supply state in which the operation of the internalcircuits thereof is not guaranteed, wherein the first or second circuitblock has an input unit which receives signals supplied from the fourthcircuit block, wherein the input unit of the first or second circuitblock has an input circuit which, in accordance with the control signalwhich was responded to when the second power supply state was instructedby the third circuit block to the fourth circuit block, causes aspecific signal level to be maintained in compliance with the operatingvoltage of the first or second circuit block irrespective of the signalsupplied from the fourth circuit block, wherein the fourth block has aninput circuit which captures as it is a signal outputted from the firstor second circuit block, and wherein the third circuit block, when thefirst or second circuit block is to be placed in the second power supplystate, also places the fourth circuit block in the second power supplystate.
 4. The semiconductor integrated circuit device according to claim1, wherein the second power supply state is a power supply cut-offstate.
 5. The semiconductor integrated circuit device according to claim1, wherein internal circuits operate in the second power supply state ata low voltage of or below the lower limit of the operating voltage. 6.The semiconductor integrated circuit device according to claim 4,wherein the first, second or fourth circuit block comprising: firstcells including first power supply lines comprising source voltage linesextending in parallel in a first direction and the ground wires ofcircuits, and first switch elements arranged in a layer including thesemiconductor substrate of such first power supply lines and disposedbetween the source voltage lines or the ground wires of circuits and thematching power supply lines of the internal circuits; second cellsincluding second power supply lines comprising source voltage linesextending in parallel in a second direction orthogonal to the firstdirection and the ground wires of circuits; third cells matching atleast one corner of an element area in which the first, second or fourthcircuit block is formed, and comprising corner power supply linesmutually connecting the source voltage lines of the first power supplylines and second power supply lines and the ground wires of circuits,and a power switch controller which is arranged in a lower layerincluding the semiconductor substrate of the corner power supply linesand controls the first switch elements of the first cells; and fourthcells matching the remaining ones of the corners and provided withcorner power supply lines mutually connecting the source voltage linesof the first power supply lines and second power supply lines and theground wires of circuits, wherein the first cells, second cells, thirdcells and fourth cells are provided in a plurality each matching thesize of the first, second or fourth circuit block, the cells surroundingthe internal circuits and making possible mutual connection of matchingpower supply lines.
 7. The semiconductor integrated circuit deviceaccording to claim 6 further comprising: fifth cells arranged matchingthe first direction in the lower layer including the first power supplylines and the semiconductor substrate of the first power supply lines,and including capacitance elements disposed over the source voltagelines and the ground wires of circuits; and sixth cells arrangedmatching the second direction in the lower layer including the secondpower supply lines and the semiconductor substrate of the second powersupply lines, and including capacitance elements disposed over thesource voltage lines and the ground wires of circuits, wherein the fifthcells are arranged alongside the first cells, and wherein the fifthcells are arranged either alongside the second cells or replacing secondcells.
 8. The semiconductor integrated circuit device according to claim7, wherein the input circuit is comprised of either a logical gatecircuit or a latch circuit.
 9. The semiconductor integrated circuitdevice according to claim 7, wherein the first, second or fourth circuitblock comprises: a combination of a first circuit formed of a MOSFEThaving a high threshold voltage, a second circuit formed of a MOSFEThaving a medium threshold voltage, and a third circuit formed of aMOSFET having a low threshold.
 10. The semiconductor integrated circuitdevice according to claim 7, wherein the input unit disposed in thefirst, second or fourth circuit block includes a level convertingcircuit matching the level of signals to be propagated.
 11. Thesemiconductor integrated circuit device according to claim 10, whereinthe logical gate circuit or latch circuit constituting the input circuitis disposed at the output side of the level converting circuit.
 12. Thesemiconductor integrated circuit device according to claim 3 furthercomprising: a fifth block equivalent to the fourth circuit block, thefifth block having a first power supply state in which the operation ofinternal circuits thereof is guaranteed in accordance with aninstruction from the third circuit block and a second power supply statein which the operation of the internal circuits thereof is notguaranteed, wherein the first circuit block, second circuit block orfourth circuit block has an input unit which receives signals suppliedfrom the fifth circuit block, wherein the input unit of the first,second or fourth circuit block has an input circuit which, in accordancewith the control signal which was responded to when the second powersupply state was instructed by the third circuit block to the fifthcircuit block, causes a specific signal level to be maintained incompliance with the operating voltage of the first, second or fourthcircuit block irrespective of the signal supplied from the fifth circuitblock, and wherein the fifth block has an input circuit which capturesas it is a signal outputted from the first, second or fourth circuitblock.